The design and manufacture of modern high performance integrated circuit devices is a complex endeavor. To ensure a desired performance level is reached, computer aided design tools such as Static Timing Analysis (STA) are used. Generally, STA refers to certain methods of computing an expected timing of a digital circuit. STA is performed on a given design usually without requiring a full on simulation.
Operational clock frequency is the traditional manner in which high-performance integrated circuits have been characterized. Gauging the ability of a circuit to operate at the specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (e.g., placement and routing), and in in-place optimizations performed late in the design cycle.
Although delay calculation timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing.
In a synchronous digital system, data is designed to move in lockstep, typically advancing one stage on each tick of the clock signal. Large designs often include a number of synchronizing elements, such as flip-flops or latches, which pass signals through their input to their output as controlled by, for example, the rising edge or falling edge of the clock signal.
A design for a synchronous digital system is primarily concerned with two kinds of timing errors. One is referred to as a hold time violation, when an input signal changes too quickly, after the clock's active transition. Another is referred to as a setup time violation, when a signal arrives too late, and misses the time when it should advance. The time when a signal arrives can vary due to many reasons. Such reasons include the fact that the input data may vary, the circuit may perform different operations, the temperature and voltage may change, there are manufacturing differences in the exact construction of each part, and the like. The objective of STA is to verify that despite these possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured. Also, since STA is capable of verifying every path, apart from helping locate setup and hold time violations, it can detect other serious problems like glitches, slow paths and clock skew.
Quite often, designers will want to qualify their design across many conditions. Behavior of an electronic circuit is often dependent on various factors in its environment like temperature or local voltage variations. In such a case either STA needs to be performed for more than one such set of conditions, or STA must be prepared to work with a range of possible delays for each component, as opposed to a single value. If the design works at each extreme condition, then under the assumption of monotonic behavior, the design is also qualified for all intermediate points.
A major trend within the field of integrated circuit design involves the use of hierarchical design techniques. Many companies utilize computer-aided design tools that employ hierarchical design techniques. Generally, hierarchical design refers to computer-aided design tools that divide a circuit netlist into a plurality of hierarchical blocks, where some blocks are more encompassing top-level blocks and other blocks or more low-level foundation blocks. There exist numerous motivations for hierarchical design, such as, the ability to allocate functional blocks to different engineering teams were different groups residing at different geographic locations. Other motivations include the ability to outsource engineering work for one or more blocks or reuse engineering work performed in designing a block in multiple subsequent designs.
As integrated circuit designs have become larger and larger, certain computer-aided design tools utilize models in order to quickly estimate the timing analysis of the constituent circuitry comprising a given block. Examples include ILMs (interface logic models) and ETMs (extracted timing models). The use of models functions by reducing the STA runtimes to more manageable levels (e.g., hours as opposed to days for some larger designs).
However, there are problems regarding the use of models in a hierarchical design flow. One problem involves the fact that the various functional blocks comprising a hierarchical design are allocated timing budgets. The timing budgets are intended to reflect the relative contribution of the timing of a particular block to the overall STA performance of the integrated circuit design. In practice, such budgets are difficult to establish accurately. Another problem involves the fact that it is difficult to manage and merge the timing constraints of lower-level blocks with the constraints of top-level blocks. For example, constraints of couple blocks are often particularly uncertain until the constraints of lower-level blocks have been firmly established.
The above problems lead to chip designers having a general lack of confidence in the STA results obtainable using hierarchical design flows. Managers are often unwilling to trust STA signoff (e.g., an assertion that the integrated circuit design meets its timing constraints) based on conventional hierarchical STA analysis. This outcome is typically a result of engineering experience, where there is little confidence the models actually represent the timing characteristics of the blocks comprising a design. One conventional solution is to simply flatten a hierarchical design such that it is represented as a single monolithic integrated circuit design (e.g., no blocks or modeling) and run conventional STA analysis on the flattened design. Once again, the problem with this solution is that as designs get larger, STA runtime can extend into several days and require very expensive computer systems. With no other options available, integrated circuit designers are often forced to pay this price.